The arrival of clock signals at various nodes in a circuit should be precisely coordinated to ensure accurate transfer of data and control information in the circuit. Clock skew is a phenomenon, primarily in synchronous circuits, in which the clock signal, generally sent from a common clock circuit, arrives at different circuit nodes at different times. This is typically due to three primary causes. The first is a material flaw which causes a signal to travel faster or slower than anticipated. The second is distance; if the signal is required to travel the entire length of a circuit, it will likely (depending upon the size of the circuit) arrive at different parts of the circuit at different times. The third is the number of non-sequential (combinational) circuits in the signal path; propagation delay through circuits such as NAND and NOR gates adds to the overall propagation delay in a given signal path.
If large enough, clock skew can cause errors to occur in the circuit or cause the circuit to behave unpredictably. Suppose, for example, that a given logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives a clock transition later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock transition, invalidating the previous data waiting there to be clocked through. This is often referred to as a “hold violation,” since the data is not held long enough at the destination flip-flop to achieve a valid output result. Similarly, if the destination flip-flop receives the clock transition earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock transition. If the data fails to reach the destination flip-flop before the next clock transition, a “setup violation” occurs, since the new data was not set up and stable prior to the arrival of the next clock transition.
Clock skew is generally influenced by one or more characteristics, including, for example, clock speed, clock driver strength, length of clock-carrying conductors, capacitance load on clock-carrying conductors, IC processing, power supply voltage level, temperature, noise, on-chip variation (OCV), number of combinational circuits, etc. The task of correcting clock skew is made more difficult by the interaction of these and other characteristics.
There are various known clock skew correction approaches. In one known skew correction technique, a “de-skew” phase-locked loop (PLL) or delay-locked loop (DLL) is employed to align the respective phases of the clock inputs at two or more components in the IC. This approach is described, for example, in the paper S. Tam, et al., “Clock Generation and Distribution for the First IA-64 Microprocessor,” IEEE J. Solid-State Circuits, Vol. 35, No. 11, November 2000, pp. 1545-1552, which is incorporated by reference herein. Unfortunately, however, this approach suffers from area, power and complexity penalties, among other disadvantages. Another technique for reducing clock skew in the IC is to tune the clock speed. This approach is described, for example, in the paper T. Kehl, “Hardware Self-Tuning and Circuit Performance Monitoring,” In Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1993, pp. 188-192, which is incorporated by reference herein. Disadvantages of this approach include a significant performance reduction due, at least in part, to slower clock speeds.
It is also known to add one or more buffers to a clock signal path when attempting to perform clock tree balancing. This approach is undesirable, however, in that the buffers increase overall power consumption and OCV in the IC, and furthermore require additional IC area, among other disadvantages.